The present invention relates generally to insulated gate field effect transistors and more specifically to an improved method of forming contacts compatible with complementary insulated gate field effect transistors fabrication methods.
For high performance, short channel field effect transistors, the source and drain regions are formed to have shallow junctions. Contact metals to the source and drain regions, for example, aluminum, can touch the edges of the shallow N-type source and drain regions and short to the P-type body. Thus, the lateral area of the N-type source and drain regions has to be sufficiently large to allow accurate placement of the aluminum contact metal substantially centered on the portions of the source and drain regions having a concentration sufficient to prevent aluminum contact of the P-type body.
For source and drain regions having a depth of under 0.1 microns, it has been suggested to make the contact to source and drain regions having a greater depth and displaced from the channel region. Because of the limitation of mask superimposing accuracy and the pattern size accuracy, there has been difficulty in locating the contact apertures over the appropriate region. Thus, the regions have been formed oversized. To solve this problem in the shallow junction MOS devices, it has been suggested by Shibata et al in U.S. Pat. No. 4,109,371 to form the deep source and drain contact regions through the contact aperture. The formation of the deep source and drain regions. generally include high temperature steps which may effect the optimized performance of the MOS device. Similar in CMOS processing, the introduction of high impurity concentration N conductivity type impurities will substantially effect the P source and drain regions requiring additional processing steps and considerations.
Thus there exists the need for a method of fabricating contacts to CMOS devices which allows reduction in the overall size of the device to increase density as well as being compatible with the CMOS processes.
The present invention overcomes the problems of the prior art by using ion implantation and low temperature activation of N-type impurities into the N-type source and drain contact areas after the formation of contact apertures through the dielectric layer which covers the substrate including the field oxide. The region formed is shallower in depth than the source and drain regions and is followed by application of conductive material, preferably aluminum, and delineation to form interconnects. If the ion implantation is formed while both the P and N source and drain regions are exposed, the implantation would introduce impurities having a concentration greater than the P body region and less than the P+ source and drain regions. Alternatively, a low temperature mask may be formed over the P source and drain regions and the N-type impurities are ion implanted in only the N-type source and drain regions. The CMOS process includes forming the field oxide by local oxidation process and the outer edge of the source and drain regions are formed aligned with the edge of the field oxide, with the depth of the field oxide exceeding the depth of the source and drain regions.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.